1. Field of the Invention
The present invention generally relates to a display drive integrated circuit for driving a display panel, and more particularly, the present invention relates to a display drive integrated circuit and method for generating a system clock signal.
A claim of priority is made to Korean Patent Application No. 10-2006-0020395, filed Mar. 3, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
FIG. 1 is a simplified block diagram of a conventional display device 100. Referring to FIG. 1, the conventional display device 100 includes a display panel 110, a timing controller 130, a gate driver circuit (i.e., a scan line driving circuit) 140, a source driver circuit (i.e., a data line driving circuit) 150, and a processor 170. The timing controller 130, the gate driver circuit 140 and the source driver circuit 150 together constitute a display drive circuit 120 of the display device 100.
As shown in FIG. 1, the timing controller 130 includes a memory 131, and outputs control signals for controlling the timing of the gate driver circuit 140 and the source driver circuit 150. The memory 131 stores display data, and outputs display data (or image data) to the source driver circuit 150 under the control of the timing controller 130.
The gate driver circuit 140 includes a plurality of gate drivers (not shown), and continuously drives scan lines G1 through GM of the display panel 110, based on the control signals received from the timing controller 130.
The source driver circuit 150 includes a plurality of source drivers (not shown), and drives data lines S1 through SN of the display panel 110, based on the display data received from the memory 131 and the control signals received from the timing controller 130.
The display panel 110 displays the display data based on signals received from the gate driver circuit 140 and signals received from the source driver circuit 150.
The timing controller 130 receives various display data and control signals from the processor 170 via an interface 160, and updates the display data stored in the memory 131.
Examples of the processor 170 include a baseband processor and a graphics processor. When the display device 100 is configured with a baseband processor, a CPU interface establishes an interface between the display device 100 and the baseband processor. When the display device 100 is configured with a graphics processor, an RGB interface (video interface) establishes an interface between the display device 100 and the graphics processor.
In the case where an RGB interface is utilized, the display device 100 receives a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal from an external source, and generates a corresponding system clock signal. The system clock signal is used to control the display data.
However, when the frequency of the dot clock signal received from the external source changes, the frequency of the system clock signal also changes, thereby degrading the display quality of the display device 100 or increasing its power consumption.